The truth table patterns for the Out and Out(carry) bits look an awful lot like XOR and AND gates, respectively. First wrote out a truth table for the Out and Out(carry) bits: In(1) In the spirit of strengthening some neural pathways I refused to look at my notes from my previous reading of ECS. So I decided to diagram an 8-bit adder with overlfow/underflow detection. That seemed like it would be easy to implement in an 8-bit adder built from an array of 1-bit adders. The point came up that you can detect an overflow or underflow by comparing the carry-in and carry-out values for the most significant bit. It’s been a while since I worked through the first part of The Elements of Computing Systems and, in preparation for the Computer Architecture course at Bradfield CS I was watching this UC Berkely lecture that touches on Two’s Complement addition. Projects Posts Building an adder with overflow detection
